In a semiconductor storage device such as a large capacity DRAM, etc., enhancement in the performance (enhancement in the speed, reduction in the power consumption, etc.) is generally achieved by dividing the memory array into plural sub-memory arrays.
FIG. 10 is a block diagam showing the main part constitution of a DRAM which shares the sense amplifier between the sub-memory arrays.
In this DRAM 100, many shared sense amplifiers (hereafter referred to simply as sense amplifier (SA)) are arranged within sense amplifier array area 103 positioned between two adjacent sub-memory arrays 101 and 102. A pair of complementary bit lines (BL) and (BL.sub.--) for each sub-memory arrays 101 and 102 are connected with respect to each sense amplifier (SA) for total of 2 pairs. These complementary bit lines (BL) and (BL.sub.--) are connected to sense amplifier (SA) for each bit line via transfer gate (TG1) or (TG2). Each gate of transfer gate (TG1) on the sub-memory array 101 side is connected to a signal line provided with shared signal (SHL1). Similarly, each gate of transfer gate (TG2) on the sub-memory array 102 side is connected to a signal line provided with shared signal (SHL2).
Sense amplifier (SA) has a CMOS amplifier composition, the power supply feed node of the NMOS amplifier thereof is connected to shared drive line (SNL) and the power supply feed node of the PMOS amplifier thereof is connected to shared drive line (SPL). Two shared drive lines (SNL) and (SPL) are connected to sense amplifier driving circuit 104 arranged on the outside of sense amplifier area 103. Also, power supply voltage feed line which is shared between sense amplifier driving circuits 104 (hereafter referred to as "shared electrical supply line (Vssa) of sense amplifier driving circuits") is arranged in the column direction.
On the other hand, selected transistor (TR) and memory capacitor (C) which compose the respective memory cell is connected at each intersecting point of complementary bit lines (BL) and (BL.sub.--) and many word lines (WL) wired in the row direction within sub-memory arrays 101 and 102. The gate of selected transistor (TR) is connected to word line (WL), the drain is connected to either of complementary bit lines (BL) and (BL.sub.--), and memory capacitor (C) is connected between the source and a shared plate line not shown in the figure.
Each word line (WL) is connected to word line driving circuit 105 which excites each word line (WL) according to the row selected signal from a row decoder not shown in the figure. The power voltage supply line shared between word line driving circuits 105 (hereafter referred to as shared electrical supply line (Vssw) of word line driving circuits is arranged in the column direction.
In a DRAM semiconductor storage device, etc., the S/N ratio (signal versus noise ratio) in the internal circuit operation decreases when the memory cell and the wiring dimension are refined and the speed is enhanced, and the capacity is enlarged by reducing the voltage. It is necessary to drive the load with a large electric current when enhancing the speed with the power supply voltage left at the reduced state but this electric current flows via a wiring resistor which increases with refinement and enlargement in the chip so that the noise generated in the signal line and the power voltage supply line increases. On the hand, there is a tendency for the voltage amplitude of the memory cell signal to decrease with low voltage operation so that S/N of the internal circuit operation decreases.
As a method for suppressing the generation of noise in order to improve said S/N, a method of achieving reduction in the operating current by restricting the area the electric current flows by dividing the memory array into sub-memory arrays as shown in FIG. 10 while on the other hand dispersing or reducing the load capacity by layering or reducing the resistance of wirings with a high load capacity such as the bit line and word line is generally used. Also, completely preventing noise generation is difficult even when these methods are used, and in a large capacity DRAM in particular, in which the memory cell signal is very weak, contriving a connection method for the wiring and preventing the effect of the noise even if noise is generated is becoming important for improving S/N.
From this point of view, the connecting relationship of the shared electrical supply line (Vssw) of word line driving circuit 105 connected to word line (WL) and shared electrical supply line (Vssa) of sense amplifier driving circuit 104 connected to complementary bit lines (BL) and (BL.sub.--) via sense amplifier (SA) and shared drive line (SNL) is vital. The reason is that noise is transmitted as induced noise via the coupled capacity at the intersecting point, etc. of the word line and the bit line but has a tendency to be more directly transmitted via the power supply voltage feed line which is shared.
However, as is well known, noise can be synchronous or asynchronous. In regard to asynchronous noise, all that is necessary is to cut it off by simply separating the power supply voltage feed lines to eliminate the noise propagation but if synchronous noise is also cut off at this time, the voltage limit with respect to erroneous operation may decrease.
For example, in the large capacity RAM in FIG. 10, there is the problem of operational defect of destroying the stored data in the nonselecteded memory cell occurring in both cases of when separating and when short circuiting shared electrical supply line (Vssw) of word line driving circuit 105 and shared electrical supply line (Vssa) of sense amplifier driving circuit 104.
The present invention was made taking said situation into consideration and aims to provide a semiconductor storage device in which said operational drawback of the stored data in the nonselecteded memory cell being destroyed does not occur easily even if the shared electrical supply line of the word line driving circuit and the shared electrical supply line of the sense amplifier driving circuit are short circuited.